Brief Review on Open-source SoCs & SoC Generators

OP

As the raise of open-source hardware and RISC-V, there are already tons of RISC-V CPU cores, however, only a few open-source SoC designs are developed. In this blog, I will cover some of open-source SoCs (System-on-chip) and their generators.

Chipyard

As the undoubtable pioneer of RISC-V, researchers from UCB have made many great contributions to the whole RISC-V ecology, and Chipyard is another incredible invention from them.
Based on their previous works about RISC-V CPUs (Rocket, BOOM) and the mighty Chisel hardware language, the Chipyard framework provides designers with a relatively complete SoC design flow.

Framework Structure

The components of Chipyard include:

• Generators for:
  • Processor Cores
  • Accelerators
  • System Components
• Tools:
  • RTL Generation (Chisel, FIRRTL)
  • Chisel Library (Dsptools)
  • Emulator for RISC-V CPU (Dromajo)
• Toolchains (for RISC-V ISA)
• Software
• Sims (Verilog Simulators)
• Prototyping (for FPGA)
• VLSI

As mentioned above, these components cover most of the SoC design flow, even some of the IC backend tools are provided.

Cores

Chipyard supports a number of well-known RISC-V cores, but the Rocket core is better supported by the framework than other cores. Just like a classic textbook for RISC-V CPU, Rocket is very standard but powerful. With the 5-stage in-order scalar architecture, it supports RV64GC ISA which gives it the capability of carrying most of common workload including running operating systems like Linux. The success of ASIC tapeout gives Rocket-chip yet another great advantage.
Other cores like BOOM, CVA6, ibex are supported as well.

SoC

The Rocket Chip is the SoC generator based on Rocket core. Here is the diagram of the basic architecture of Rocket Chip:

Like most of SoCs, many components are connected by a bus to build up the complex system. The mainly supported bus is TileLink, which is also developed by UCB themselves, but support larger range of components and hardware, AXI-TL bridges are included in the SoC.
Accelerators like Hwacha and Gemmini are supported by the framework, and can be easily integrated into SoC.

Summary

Chipyard is a really ambitious and powerful framework. For those who want to design and customize a SoC with high performance and rich functionality, it’s a tier-1 choice.

PULP Platform

Unlike Chipyard, PULP Platform mainly focused on small cores with 32-bit word length and fewer pipeline stages, while still offers an option of CVA6, a 64 bit 6-stage CPU.

The platform consists of multiple projects: cores, peripherals, accelerators… all kinds of components in SoCs can be found here. In the platform, there are some SoC designs with different performances and sizes, from single core to Multi-core, than to Multi-cluster.

Framework Structure

PULP Platform is more like a collection of RISC-V projects, and they are designed using Verilog and SystemVerilog, which are quite traditional but highly optimized. Most of their github repos are hardware designs.

Cores

For almost every kind of purposes, from IoT to HPC, PULP gets a right core for you, and there are more in PULP’s github repos.
One of the unique core adopted by PULP is RI5CY. In the introduction of RI5CY in this slide, some features were mentioned, including the support for custom instruction set extensions.
The goal of RI5CY is to achieve energy-efficient signal processing with low overhead extensions, which leads to the design of series of custom instructions such as:

• Hardware Loops
• Post-incrementing load and store
• Multiply-Accumulate
• ALU extensions (min, max, absolute value, …)

The core has a competitive performance which beats the ARM Cortex-M4 core in many benchmark kernels.
However, custom instructions bring the need of custom GCC compilers, which could be a tricky problem for others to modify the core.

SoC

PULPino and PULPissimo are two SoC platforms using RI5CY core.
PULPion is a single core SoC, information about PULPino is in the same slide mentioned above. The architecture of SoC is rather simple, it contains all the basic components for a SoC with AXI4 bus connecting them with each other. It’s a good educational example as a minimal system, but can be easily extended.
PULPissimo shows how could PULPion be extended to a more powerful system. Here is a the diagram of its architecture:

With higher completeness and complexity, PULPissimo supports integration of hardware accelerators (Hardware Processing Engines), which gives it the capability of dealing with complex signal processing operations and AI kernels.

Summary

Comparing to Chipyard, PULP platform has some really great SoC projects in IoT and low Power design, and the open-source hardware IPs including AXI bus, peripherals and cores. Nonetheless, as most of hardware are designed directly(using SystemVerilog) without generators, the lack of supports for customizations could be a problem.

LiteX

LiteX is a open-source SoC builder framework grown up from the community. Targetting at creating systems based on FPGAs conveniently, the framework has integrated many awesome small projects. A complete work flow from upper level designs to FPGA bitstreams is provided in the open source manner. Mixed languages support is a unique feature of LiteX, which largely increases the agility of SoC development.

Framework Structure

LiteX provides all the common components required to easily create an FPGA Core/SoC:

• Hardware Components such as Buses, IP cores and CPU cores

• Debug infrastructure

• Simulation through Verilator

• Backends

                          +---------------+
                          |FPGA toolchains|
                          +----^-----+----+
                               |     |
                            +--+-----v--+
           +-------+        |           |
           | Migen +-------->           |
           +-------+        |           |        Your design
                            |   LiteX   +---> ready to be used!
                            |           |
  +----------------------+  |           |
  |LiteX Cores Ecosystem +-->           |
  +----------------------+  +-^-------^-+
   (Eth, SATA, DRAM, USB,     |       |
    PCIe, Video, etc...)      +       +
                             board   target
                             file    file

Unlike others, LiteX builds up a ecosystem for SoC design, making it a lot easier than tradtional approaches.
The high flexibility of the framework enables different options for many details of SoCs, especially for ISAs (including RISC-V and x86) and interfaces (including PCIe, SATA and Ethernet). The variety of IP cores supports the creation of SoCs that powerful enough for actual applications, rather than simple toy projects.

Python-based hardware design tools like Migen are integrated, and a set of well maintained documents/wikis is offered.

Cores

CPU cores with different ISAs are provided by the framework, and different variants for each cores are provided as well. From the documents, it seems the VexRiscv is one of the most supported and feature-rich cores in LiteX, which is further discussed in next section.

Multi-core system support is another great thing in LiteX. This gives users the power of creating Linux capable SoCs.

SoC

A multi-core Linux capable SoC is set as a example of LiteX SoC:

As the framework is mainly based on Python, the generation of SoCs is very agile. Simulators for both CPU cores and SoCs are included, which enables debugging and testing without FPGA boards.

Summary

There are a lot of novel things in Litex, which differs it from other frameworks mentioned. While most of academic frameworks are lacking of good tutorials, user-friendly interactions and active maintenance, LiteX builds up a lively community that warmly welcomes new users, and some research papers (e.g. CFU-Playground) have shown the LiteX’s potential of academical uses.

Can’t wait to have a try? Just clone it and run the setup script!

Briey SoC & Murax SoC

Briey and Murax are both a part of VexRiscv project, which is a FPGA friendly 32 bit RISC-V CPU implementation using Spinal HDL, a language very similar to Chisel. These two SoCs serve as a sort of demonstrations of extending VexRiscv into a complete system, but they do benefit from highly configurable hardware generation provided by Spinal HDL.

Framework Structure

Based on Spinal HDL, the generators for SoCs are written into Scala codes, CPU configuration and SoC configuration are designed into classes with parameters. To generate SoCs, you only need to pass configurations to a generation function, then the Verilog codes will be emitted.

Cores

VexRiscv is a RISC-V CPU implemented in Spinal HDL, it has one of the highest customization ability among open-source RISC-V cores. Supported instruction sets, pipeline stages, caches, FPUs, every part of microarchitecture is configurable, leaving a huge space for users to modify depending on their own needs. The plugin feature of VexRiscv allows users to add their custom hardware directly into the CPU architecture, which could be potentially used for accelerations.

SoC

Briey and Murax serve as the demostrations of extending VexRiscv into a complete system.
In Briey, the interconnection between host cpu and other components is under AXI protocol, and all components are designed using Spinal HDL. Beside the configurable options of VexRiscv, Briey SoC also has a wide range of options including memory sizes and peripheral settings.

Murax is a small SoC that can fit into a FPGA with less than 3000 logic cells. Aiming to minimize the area, Murax only keeps the basic components for a SoC to act like a microcontroller. The configurable options are not as many as Briey but still sufficient for some simple customizations.

Summary

The flexibility of VexRiscv and Spinal HDL gives a great freedom to users to design the SoC they want, but also leaves the problem of finding optimal solutions to them, which could be a challenge. But for those who are willing to explore this large design space, Briey and Murax are perfect playgrounds.

ED

That’s all guys! It’s hard to dig out every attmpts people made to build open-source SoC frameworks, but I hope this blog could open up some options for you when you try to design your own SoC, or bravely, build your own SoC framework.

Thanks for reading!

References

riscvarchive/riscv-cores-list

aolofsson/awesome-opensource-hardware